Standard Speed SCL High Count Register
IC_SS_SCL_HCNT | This field must be set before any I2C bus transaction can take place to ensure proper I/O timing. It sets the SCL clock high-period count for Standard Speed. This field is written only when the I2C interface is disabled which corresponds to the I2C_ENABLE[ENABLE] bit is set to 0x0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. Note: This field must not be programmed to a value higher than 65525, because I2C uses a 16-bit counter to flag an I2C bus IDLE condition when this counter reaches a value of I2C_SS_SCL_HCNT + 10. |